1. Field of Invention
The present invention relates generally to integrated circuits and methods of fabricating such circuits and, more specifically, NAND flash memory cells and methods of fabrication thereof.
2. Description of the Prior Art
A NAND-structured memory string has several floating gate memory transistors (typically 8 or 16) connected in series between two select gates. The area occupied by the memory transistors is called the core region. The control gates of the memory transistors are connected to other parallel NAND strings by wordlines to form a NAND memory array. The parallel NAND strings are separated by a core field oxide region.
NAND flash memory strings are typically fabricated using a xe2x80x9cdual-gate oxidationxe2x80x9d process where the gate oxide of the select transistors is first thermally grown on a silicon substrate. The select transistor areas are then masked with photo-resist and the gate oxide in the core region is etched away, typically in a buffer oxide etch process, to expose the silicon substrate. The photo-resist is then removed and the gate oxide is thermally regrown to define the final gate oxide thickness of the two select gate transistors and the sixteen floating gate memory transistors. This approach resulted in a select transistor gate oxide thickness of 150xc3x85-180xc3x85 and a memory transistor gate oxide thickness of 85 xc3x85-105 xc3x85, as illustrated in FIG. 1. FIG. 1 shows a select transistor area 12 and a core transistor area 13. The oxide layer 14 grown over the P-well 11 is thicker in select transistor area 12 than in core transistor area 13. The select gate oxide is thicker than the core tunnel oxide in order to prevent band-to-band tunneling current between source/drain region 17 and P-well 11. In order for the select gate to function in spite of the thick select gate oxide, source/drain region 17 must be doped.
Making the select gate oxide thicker than the core tunnel oxide adds several steps to the fabrication of the NAND string. Additional processing steps increase the cost of fabricating the device. Further, these additional steps can affect the reliability of the NAND string. For example, the masking and etching steps can leave contaminants on the surface of the NAND string or introduce defects into the NAND string. Such contaminants and defects can degrade the core tunnel oxide and, as a result, lead to poor reliability of the memory cells. Also, the masking step increases the amount of space required for the NAND string because imprecision inherent in any masking step requires that a tolerance area be masked in addition to the select gate area.
The present invention provides a single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the 16 floating gate memory transistors are fabricated in a single oxidation step. The oxidation process can be either dry, wet or nitrided. The two select gate transistors and the floating gate memory transistors have the same oxide thickness (85 xc3x85-105 xc3x85). In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentration of 1013-1014/cm2.
Several advantages result from this method for fabricating the NAND memory arrays. First, eliminating a masking step, eliminating a thermal cycle, and eliminating associated cleaning steps simplifies the fabrication of the device, thus lowering the cost and allowing fabrication of a more compact device. Also, elimination of the masking step improves the isolation property of the core field oxide layer separating the strings, which reduces program disturb and increases the coupling ratio between the floating gate and the control gate in the core memory cells. Further, a NAND string formed by the single tunnel gate oxidation process can be programmed or erased at a lower voltage. In addition, the medium doped source/drain region used in the single tunnel gate oxidation process reduces the band-to-band tunneling current.